Whizz Systems' Guide to PCIe-6

Signal Integrity

What are the key factors affecting signal integrity in PCIe Gen 6, and how are they mitigated?

In PCIe Gen 6, several key factors impact signal integrity, and addressing these challenges is crucial for maintaining reliable high-speed data transmission. One significant factor is transmission line effects, where impedance mismatches, reflections, and distortion can occur. To mitigate this, meticulous PCB design practices are employed, including controlled impedance traces and proper termination techniques. Channel loss and attenuation are other factors that demand attention. Advanced equalization techniques, such as decision feedback equalization (DFE) and continuous time linear equalization (CTLE), are implemented to compensate for signal loss during transmission through PCB traces and connectors.

Crosstalk, the interference between adjacent traces, is a persistent challenge. Design strategies involve maintaining proper spacing between traces, using shielded connectors, and leveraging signal integrity simulations to minimize crosstalk effects. Jitter, or timing variations in signals, is also a concern. To address this, PCIe Gen 6 incorporates high-quality clocking mechanisms, low-jitter oscillators, and advanced clock data recovery (CDR) circuits to reduce timing uncertainties.

Power integrity plays a crucial role in signal integrity, as power fluctuations and noise can impact the overall system. Power distribution networks, decoupling capacitors, and power management techniques are implemented to mitigate this. Connector and interconnect quality are essential, and utilizing high-quality connectors, impedance-matched interconnects, and thorough testing helps ensure reliable signal transmission.

Furthermore, advanced equalization techniques and forward error correction (FEC) are integrated into PCIe Gen 6 to address the challenges associated with higher data rates. These technologies enhance the reliability of data transmission by compensating for signal distortions and detecting/correcting errors in real time. The choice of advanced materials with low dielectric constant and low loss tangent in PCB construction is also considered to minimize signal distortion.

Additionally, advanced packaging techniques, such as micro bumping and Chip-on-Wafer-on-Substrate (CoWoS), reduce parasitic effects and enhance signal integrity. Collectively, these strategies underscore the comprehensive approach taken in PCIe Gen 6 to ensure robust signal integrity in the face of increasing data rates and performance requirements. For the most accurate and detailed information, consult the official documentation provided by the PCI-SIG.

How do you calculate and manage signal loss and jitter in a PCIe Gen 6 system?

In a PCIe Gen 6 system, managing signal loss and jitter involves a multifaceted approach. Signal loss is addressed through careful transmission line analysis, ensuring controlled impedance traces, and establishing an insertion loss budget that considers losses in connectors, cables, and PCB traces. Advanced equalization techniques like decision feedback equalization (DFE) and continuous time linear equalization (CTLE) are implemented in receivers to compensate for signal loss and distortion.

On the other hand, jitter management requires using high-quality clock sources with low jitter, advanced clock data recovery (CDR) circuits, and implementing adaptive CDR techniques. Designers establish a jitter budget, employ simulation tools for analysis, and apply filtering and conditioning methods such as phase-locked loops (PLLs) to reduce unwanted jitter components. Real-time monitoring tools are utilized to continuously assess and adjust for system variations.

Additionally, compliance testing, bit error rate (BER) testing, and eye diagram analysis play crucial roles in validating signal integrity and ensuring the system meets PCIe Gen 6 specifications. This comprehensive approach, coupled with real-world testing, contributes to robust and reliable high-speed data transmission in PCIe Gen 6 systems. Designers should refer to the PCI-SIG's official PCIe Gen 6 specifications for accurate guidelines and requirements.

What is the role of eye diagrams and bit error rate testing in PCIe Gen 6 signal integrity validation?

In PCIe Gen 6 signal integrity validation, eye diagrams and Bit Error Rate (BER) testing are indispensable tools. Eye diagrams illustrate signal quality, portraying characteristics like jitter, noise, and timing margins. This visualization is crucial for assessing the openness of the eye within defined voltage and timing thresholds, ensuring reliable signal reception. In parallel, BER testing involves comparing transmitted and received bit sequences, quantifying the accuracy of data transmission. Low BER values indicate a high level of signal integrity and system reliability.

These tools are integrated, with information from eye diagrams guiding the understanding of factors contributing to observed bit errors during BER testing. Together, they provide a comprehensive evaluation of signal quality and aid in the optimization of PCIe Gen 6 systems for high-speed data transmission, meeting stringent performance requirements. Regular testing and analysis using these tools contribute to the development of robust and reliable PCIe Gen 6 communication links.

Power

What challenges arise in managing power distribution in PCIe Gen 6 compared to earlier versions?

Managing power distribution in PCIe Gen 6 presents several challenges compared to earlier versions. One notable challenge is the potential increase in power demands as a consequence of higher data rates and enhanced performance capabilities inherent in PCIe Gen 6 components like advanced processors and accelerators. This necessitates careful consideration of power management strategies to ensure optimal system stability and performance. Dynamic power delivery becomes crucial to accommodate varying workloads efficiently, and staying within reduced power budgets due to thermal constraints and energy efficiency considerations poses another challenge.

Additionally, with the higher frequencies associated with PCIe Gen 6, maintaining power integrity becomes more complex, requiring robust power distribution networks to handle increased frequencies without introducing noise or voltage fluctuations. Voltage regulation and noise control mechanisms must be advanced to address the performance demands while minimizing voltage variations. Electromagnetic interference (EMI) becomes more pronounced at higher data rates, emphasizing the need for effective EMI mitigation strategies to comply with electromagnetic compatibility (EMC) standards. Achieving high power efficiency remains a constant challenge, requiring innovations in power delivery architectures, voltage regulation, and component efficiency.

Moreover, the adoption of advanced packaging techniques, like Chip-on-Wafer-on-Substrate (CoWoS) or 2.5D/3D integration, introduces new complexities in power distribution, necessitating innovative solutions. Designers must stay informed about official specifications and guidelines provided by the PCI-SIG for PCIe Gen 6 to address these challenges effectively and ensure optimal power distribution in high-speed serial communication systems.

What techniques can be employed to minimize voltage droops and ensure stable power delivery in PCIe Gen 6 systems?

Ensuring stable power delivery in PCIe Gen 6 systems requires a multifaceted approach, employing various techniques to minimize voltage droops. Dynamic Voltage and Frequency Scaling (DVFS) allows for adaptive adjustments to voltage and frequency based on workload demands, optimizing power consumption and mitigating voltage droops during varying workloads. Advanced voltage regulators with fast response times and tight voltage regulation characteristics are instrumental in swiftly adjusting output voltage to minimize droops. Strategic placement of decoupling capacitors across the PCB acts as a buffer, absorbing transient currents and stabilizing voltage levels. Power gating techniques selectively disable power to inactive components, reducing overall power consumption and minimizing droops. Active power management involves real-time monitoring and control of power consumption, making dynamic adjustments to voltage levels.

Predictive voltage scaling algorithms anticipate workload changes, proactively adjusting the voltage to prevent droops. Transient voltage suppressors and low-ESR capacitors protect against spikes and enhance the system's ability to maintain stable voltage levels. Optimizing power plane design on the PCB reduces impedance and inductance, enhancing the power distribution network's responsiveness. Fast-response voltage regulators and thorough simulation and analysis using dedicated tools help identify and address potential droop issues in the power delivery network. Implementing these techniques collectively ensures a stable power supply, meeting the demanding requirements of PCIe Gen 6 systems and contributing to reliable high-speed data transmission. Designers should refer to the PCI-SIG's official PCIe Gen 6 specifications for precise guidelines and considerations.

Layout Design

What considerations should be taken into account when designing the PCB layout for PCIe Gen 6?

Designing the PCB layout for PCIe Gen 6 demands meticulous attention to various critical considerations to guarantee optimal signal integrity and high-speed communication. Controlled impedance is paramount, necessitating precise impedance matching for high-speed differential pairs to minimize signal reflections. Following recommended routing guidelines is crucial, encompassing considerations like avoiding sharp bends, maintaining consistent trace lengths, and minimizing crosstalk. Establishing an efficient power distribution network with low impedance paths, including solid ground planes for a low-impedance return path, contributes to reducing electromagnetic interference. Careful placement of vias, adherence to PCIe Gen 6 specifications for connector positioning, and the incorporation of decoupling capacitors near high-speed components are essential for mitigating signal integrity issues.

Ensuring equalized channel lengths for SerDes lanes and addressing thermal considerations, including proper spacing and thermal management techniques, are vital aspects of the layout. Designers should also focus on electromagnetic compatibility (EMC) and electromagnetic interference (EMI) compliance, implementing shielding techniques and simulation tools to model signal integrity.

Conducting compliance testing verifies adherence to PCIe Gen 6 specifications, providing assurance that the PCB layout meets the necessary electrical and mechanical requirements for reliable high-speed data transmission. Regular reference to the official PCIe Gen 6 specifications provided by the PCI-SIG is essential to align the design with industry standards and best practices.

What is the main difference between PCIe 5 and 6 from a design point of view?

The primary differences between PCIe Gen 5 and PCIe Gen 6 are expected to involve improvements in data transfer rates, bandwidth, and overall performance. PCIe Gen 5 uses PAM4 (Pulse Amplitude Modulation with 4 levels) for encoding, while PCIe Gen 6 is expected to continue using PAM4. PAM4 is a modulation scheme that encodes multiple bits per symbol, allowing for higher data transfer rates compared to traditional binary encoding (which encodes one bit per symbol).

The primary differences between PCIe Gen 5 and PCIe Gen 6 are expected to involve improvements in data transfer rates, bandwidth, and overall performance. PCIe Gen 5 uses PAM4 (Pulse Amplitude Modulation with 4 levels) for encoding, while PCIe Gen 6 is expected to continue using PAM4. PAM4 is a modulation scheme that encodes multiple bits per symbol, allowing for higher data transfer rates compared to traditional binary encoding (which encodes one bit per symbol).

It's important to note that specifications and details may evolve, and the most accurate and up-to-date information can be obtained from the PCI-SIG (PCI Special Interest Group), which oversees the development of the PCIe standard.

Here are some general expectations based on the trends seen in previous PCIe generations:

Bandwidth

PCIe Gen 5: Provides higher bandwidth compared to previous generations, allowing for increased data throughput between the CPU and connected devices.

PCIe Gen 6: Anticipated to offer even greater bandwidth, enabling faster communication between components and supporting the increasing demands of modern applications and workloads.

Clocking Considerations

Clocking becomes more challenging at higher data rates. Designers must pay attention to clock distribution, jitter, and skew to ensure that devices can synchronize properly.

Backward Compatibility

Designers should consider backward compatibility with previous PCIe generations. Systems might include a mix of PCIe Gen 5 and Gen 6 devices, and the design should account for seamless interoperability.

Component Selection

Careful selection of components, including transceivers, switches, and connectors, is vital to ensure compatibility with PCIe Gen 6 and to maximize performance.

What considerations should be taken into account when designing the PCB Library footprints for PCIe Gen 6?

Designing the PCB (Printed Circuit Board) library footprints for PCIe Gen 6 involves careful consideration of the electrical, mechanical, and manufacturing requirements to ensure proper functionality and compatibility. Ensure that the footprints have the correct dimensions and comply with PCIe Gen 6 electrical and mechanical requirements. Respect the keep-out zones specified in the PCIe Gen 6 standards to maintain signal integrity.

Do we need to add the cut-out under AC caps for Gen6 signals?

Based on our previous experience, we need to add the cut-out underneath AC caps to reduce the capacitance (created by the component pads) and minimize the impedance discontinuity. The cut-out is also helpful in increasing the inductance.

What would be the GSSG via structure and antipad geometries for PCIE Gen6?

GSSG via pattern and anti pad geometries for PCIe Gen6 are designed to align with signal integrity principles and minimize electromagnetic interference. Using a GSSG via pattern with an antipad is a recommended practice. The antipad plays a crucial role in maintaining isolation between the signal via and the surrounding ground plane for reducing the risk of crosstalk and signal distortion.

GSSG via pattern and anti pad geometries for PCIe Gen6 are designed to align with signal integrity principles and minimize electromagnetic interference. Using a GSSG via pattern with an antipad is a recommended practice. The antipad plays a crucial role in maintaining isolation between the signal via and the surrounding ground plane for reducing the risk of crosstalk and signal distortion.

What are the dimensions of the via pad stack to be used for PCIE Gen6 signals?

As per our experience in the Gen4 and 5 layouts, an 8-mils drill with an 18-mils pad can be suitable for most designs. However, pre-layout simulation can drive this calculation, and post-layout simulation can only be used for confirmation.

What are the trace spacing rules for the PCIE Gen6 signals within and outside the group?

Around 30 mil spacing is recommended for PCIE Gen6 signals.

What are the length-matching rules for Gen6 PCB boards?

Because the speed and delays have not changed, we can follow the matching rule of PCIE gen5, e.g., phase tuning in 1 mil.

What are Ground plane recommendations under PCIE Gen6 edge finger?

To support the high-speed signals in PCIE gen5 and 6 for an Add-in Card, inner ground plane layers must be under the PCIE signals for GND reference.

These GND plane recommendations provided good ground Plane shielding for TX and RX pins.

GND plane cut is recommended under the pin area for the edge finger to avoid crosstalk in the Z axis due to the TX and RX pins on the Top and Bottom sides. In addition, at least 2 full deepest inner Ground planes are recommended from the middle of the stackup. For example, the GND metal of layers 5 and 6 should be under the finger pins out of a 10-layer stackup. In the case of a high-layer count board, multiple deep planes may lie within this region.

What is Fingertip Ground Vias, and how is it implemented in PCIE Gen6 PCB board layout?

It is a row of plated vias to be connected to the inner layer ground plane along the bottom of the edge-fingers in the high-speed region comprising pins A12/B12 and beyond. A ground strip must be implemented to join all the Fingertip South Vias on the first inner layer on each side of the board.

What is the recommended Routing Layer for PCIe Gen6 traces?

Well, routing layer preference depends on variant factors like pin assignment, coating material surrounding circuits, etc… It would be recommended to use microstrip traces with adequate spacing from noisy circuits as they don’t introduce any signal loss inserted due to VIAs.

What would be the recommended Routing pattern for PCIE Gen6 Traces?

It is expected to have a higher maximum theoretical data transfer rate per lane, likely doubling the speed of PCIe Gen 5. At this speed, Curves are preferred over sharp bends in the traces to overcome signal integrity issues. These high frequencies can lead to signal distortions, reflections, and crosstalk in sharply bent traces, affecting overall performance and reliability. Routing with gentle curves helps maintain signal integrity by reducing impedance mismatches and minimizing signal distortions.

Manufacturing

Why do we need a dielectric material with low Dk and Df?

High-frequency and high-speed PCBs must have dielectric materials that allow for low and stable dielectric constants (DK) and dielectric loss factors (Df).

Fiberglass and epoxy are frequently chosen as base materials. However, we cannot always find options that meet our DK and Df requirements. In such cases, we evaluate whether their application concerns the transmission of high-speed signals. If so, we shall prioritize low Df over low DK. However, the reverse is true for high-frequency signals.

As for the PCIe 5.0, we must consider the typical operating conditions for the PCIe 6.0 builds too as DK and Df rise with temperature increases. They’ll also rise when the base materials experience moisture. Thus, we must select ones with low absorption factors

Why low-profile (HVLP) copper?

Although this may compromise the bond strength of multilayers with each other high-frequency signaling makes us go for the LP (Low Profile), VLP (Very Low Profile), and HVLP (Hyper Very Low Profile) copper types to cater to the losses caused by the skin effect which increases manufacturing cost.

Are there any manufacturing considerations?

Fabricators opt for hard gold plating as a surface finish treatment on PCIe fingers. Usually, surface finishes are applied after the application of LPI solder mask coating, but for a design like PCIe 5.0 and 6.0, fabricators have to customize their plating process, which increases the design complications and sometimes the manufacturing cost as well.

For older PCIe Generations, the method of tie & bus bars was used to electroplate hard gold which had no process customization but for a design like Gen 5.0 and 6.0, fabricators have to electroplate hard gold even before etching process which increases the height of the base copper weight of outer layers and drives the need of larger copper feature spacing on outer layers for better etching yield.

Thermal Management

What challenges may arise in thermal management in PCIe Gen 6 compared to earlier versions, and how can different techniques mitigate them?

PCIe Gen 6 supports higher data transfer rates than its predecessors and can lead to increased heat generation. The choice of cooling solutions and their design plays a significant role in managing heat generated by PCIe Gen 6 devices. So, enhanced cooling solutions, including advanced heatsinks, heat spreaders, fans, or liquid cooling, can help dissipate heat efficiently.

Mechanical Design

What considerations should be taken into account when designing the mechanical design for PCIe Gen 6?

Ensure that the mechanical design aligns with PCIe Gen 6 form factor specifications. Consider whether it's a standard form factor like ATX, or if it needs to fit within a specific enclosure or system design. Similarly, the layout should be designed to facilitate optimal airflow, ensuring that PCIe Gen 6 components receive sufficient cooling and have access to cooling solutions. In addition, developing accurate 3D models of electrical and mechanical components to assist with mechanical design and ensure compatibility with CAD software used in the overall product design.